Hardware Modeling using Verilog

Hardware Modeling using Verilog

Rs.2,499.00

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SKU: cid_11220 Category: Tags: , ,
About the course

This course will help you to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.

This course covers in detail, the digital circuit design flow, Verilog variables, operators and language constructs. The course also covers the process of modeling combinational and sequential circuits using Verilog. The course then introduces you to Verilog test benches and design simulational along with behavioral and structural design modeling. After that, the course covers various modeling issues like pipelining, memory, etc. and processor design using Verilog.

Learning Outcomes

After completing this course, you will be able to:

  • Understand Verilog and its various aspects.
  • Develop self-confidence in modeling hardware using Verilog.
  • Address the issues in hardware modeling efficiently.
  • Understand the design process and processor design process.
  • Write test benches and perform the simulation of the circuits easily and efficiently.
  • Boost your hireability through innovative and independent learning.
  • Get a certificate on successful completion of the course.
Target Audience

The course can be taken by:

Students: All students who are pursuing any technical/professional courses, and interested in learning hardware design and modeling.

Teachers/Faculties: All teachers/faculties who wish to acquire new skills or improve their efficiency in hardware design and modeling using Verilog.

Professionals: All working professionals, who wish to upgrade their skills by learning hardware modeling using Verilog language.

Why learn Hardware Modeling Using Verilog?

Verilog and VHDL are the two top HDLs used for hardware logic design. Verilog HDL is easy to learn and easy to use, due to its similarity in syntax to that of the C programming language. Career prospects are very bright in the field of hardware design using Verilog HDL. Companies into VLSI, design integrated circuits is used by almost every domain in the industry. These companies design chips and manufacture them in large quantities. In simple words, VLSI circuits are everywhere from your computer to your car, your brand new state-of-the-art digital camera, cell phones, and whatever electronics item you have. The designs are mostly used for small transistor - count precision circuits such as amplifiers, data converters, filters, phase-locked loops, and sensors.

Course Features
  • 24X7 Access: You can view lectures as per your own convenience.
  • Online lectures: 21 hours of online lectures with high-quality videos.
  • Updated Quality content: Content is latest and gets updated regularly to meet the current industry demands.
Test & Evaluation

Each lecture will have a quiz containing a set of multiple choice questions. Apart from that, there will be a final test based on multiple choice questions.

Your evaluation will include the overall scores achieved in each lecture quiz and the final test.

Certification

Certification requires you to complete all the lectures, quizzes, and the final test. Your certificate will be generated online after successful completion of course.

Topics to be covered
  1. HMUV-Module-01
    • What are the course objective and the VLSI design process and what are the First Planar IC (1961) and Intel Nehalem Quad Core Die?
    • Moore's Law and VLSI design flow?
    • Why there is a need to use Computer Aided Design (CAD) tools and what are the two Competing HDLs and what is the Simplistic View of Design Flow and its Step?
    • What are the data path, logic and physical design and manufacturing and what are the other steps in design flow?
    • What are the course objective and the VLSI design process and what are the First Planar IC (1961) and Intel Nehalem Quad Core Die?
  2. HMUV-Module-02
    • How to represent a design and what are its different viewpoints?
    • What are the Behavioral representation and its examples?
    • What are the Structural representation and its examples?
    • What are the Physical representation and its examples?
    • Moore's Law and VLSI design flow?
  3. HMUV-Module-03
    • How to get started with Verilog and why Verilog is used?
    • What can be done after specifying the system in Verilog?
    • What are the simulation and synthesis tools?
    • How to simulate Verilog Module(s)?
    • Why there is a need to use Computer Aided Design (CAD) tools and what are the two Competing HDLs and what is the Simplistic View of Design Flow and its Step?
  4. HMUV-Module-04
    • What are VLSI design cycle and physical design and what are the various design styles and which one to use?
    • What is the Field Programmable Gate Array (FPGA), it's example and working?
    • What is the FPGA Design Flow?
    • What are the data path, logic and physical design and manufacturing and what are the other steps in design flow?
  5. HMUV-Module-05
    • What is the Gate Array Design style and it's aspects?
    • What is the Standard Cell Base Design style and it's aspects?
    • What is the Full Custom Design Style and it's aspects?
  6. HMUV-Module-06
    • What is the concept of Verilog "Module"?
    • What are the different data types in Verilog?
    • What is Net data type?
  7. HMUV-Module-07
    • What is Register data type?
    • What is a "reg" data type?
    • What is "integer", "real" and time data type?
    • What are Vectors?
    • What are Multidimensional arrays and memories, how constant values are specified and what are parameters?
  8. HMUV-Module-08
    • What is the predefined set of logic gates in Verilog?
    • What are the different primitive gates in Verilog?
    • Why 'timescale' directive is used and how connectivity is specified during instantiation?
    • What are the various issues in Hardware Modeling?
  9. HMUV-Module-09
    • What are the various arithmetic and logical operators in Verilog?
    • What are the different relational and bitwise operators in Verilog?
    • What are the reduction operators and how they work?
    • What are concatenation and replication operators?
    • What is the precedence of the operator?
  10. HMUV-Module-10
    • What is behavioral and structural modeling?
    • How Is Hierarchical modeling of a 16-to-1 multiplexer explained using pure behavioral modeling?
    • How to implement 16-to-1 and 4-to-1 multiplexers using 4-to-1 and 2-to-1 multiplexers respectively?
  11. HMUV-Module-11
    • What is the behavioral description of a 16-bit adder?
    • How a 16-bit adder is modeled using 4-bit adder blocks (with ripple carry between blocks) and how 4-bit adders are modeled as the ripple carry adder?
    • How are 4-bit bit adders modeled using Carry Lookahead principle?
  12. HMUV-Module-12
    • What are the different styles of description in Verilog and what is Dataflow style?
    • How to model multiplexers, an array of multiplexers, and decoder using "assign"?
    • How to model level sensitive latch and SR latch using "assign"?
  13. HMUV-Module-13
    • What are the behavioral design and "initial" block?
    • What is the "always" block, its basic syntax and what are some rules to be followed?
    • What are the various sequential statements (like begin…end, if…else, case, casez and casex) in Verilog and their examples?
  14. HMUV-Module-14
    • What is a "while" and "for" loop in Verilog?
    • What is a "repeat" and "forever" loop in Verilog?
    • What are the various ways in which event expressions can be specified with examples?
  15. HMUV-Module-15
    • What are the various combinational and sequential logic examples for illustrating procedural assignments?
    • What are the different the scenarios in which a case statement can generate a sequential circuit upon synthesis and how to combine “assign†and procedural blocks inside the same module?
  16. HMUV-Module-16
    • What do you mean by Procedural Assignment and Blocking / Non -Blocking Assignments
    • What is Blocking Assignment and it's example?
    • What is Non- Blocking Assignment and it's example and what are the rules to be followed?
  17. HMUV-Module-17
    • How 8-to-1 multiplexer, synchronous up-down counter and n-bit counter are modeled using blocking and non-blocking assignments?
    • How to use more than one clocks in a module and how to use multiple edges of the same clock?
    • How is a ring counter modeled using blocking and non-blocking assignments?
  18. HMUV-Module-18
    • What are the various examples of modeling using blocking and non-blocking assignments?
  19. HMUV-Module-19
    • How blocking and non-blocking assignments are mixed in procedural blocks?
    • What is "generate" and "genvar" in Verilog?
    • How to create a bitwise exclusive or and N bit ripple carry adder using "generate"?
  20. HMUV-Module-20
    • What are User Defined Primitives (UDP) and what are the rules and guidelines for using them?
    • How is the modeling of combinational circuits done?
    • How is the modeling of sequential circuits done?
  21. HMUV-Module-21
    • What is a Verilog test bench and it's featured?
    • How to write test benches and what are the various simulator directives included in the test bench?
    • How are simulator directives used in a 2-bit equality checker adder example?
  22. HMUV-Module-22
    • How to write the test bench for a full adder?
    • How to write the test bench for a 4-bit shift register?
    • How to write the test bench for a 7-bit binary counter?
  23. HMUV-Module-23
    • What is a Finite State Machine (FSM) and how FSM can be represented?
    • What are Mealy and Moore machine and their pictorial depiction?
    • What is the example of three lamps?
  24. HMUV-Module-24
    • How to design a serial parity detector?
    • How to design a sequence detector?
    • How to design a sequence detector for bit pattern "101010"?
  25. HMUV-Module-25
    • What is a data path and control path?
    • How to design data and control path for repeated addition example?
    • How to write the Verilog coding for data and control path designs?
    • How to write the test bench for the example?
  26. HMUV-Module-26
    • What is a better style of modeling data/control path?
    • How to design the data and control path for the example of GCD computation?
    • How to write the Verilog coding for data and control path designs?
    • How to write the test bench for the designs and what is the alternate approach for modeling control path?
  27. HMUV-Module-27
    • What is Booth's multiplication and it's example?
    • How to design the data and control path for Booth's multiplication example?
    • How to write the Verilog coding and test bench for data and control path designs?
  28. HMUV-Module-28
    • What are the synthesis rules for combinational logic?
    • What are the styles for synthesizable combinational logic and it's examples?
    • What is the difference between function and task and what are the constructs that need to be avoided for combinational synthesis?
  29. HMUV-Module-29
    • What are the naming conventions to be followed?
    • What are comments and different coding styles to be followed and what is module partitioning?
    • What are the general coding techniques and General Guidelines For Synthesis?
  30. HMUV-Module-30
    • How to Model Memory and it's example?
    • How to Initialize Memory and it's examples?
    • Why "inout" datatype shouldn't be used and how to use bidirectional lines in the hardware (ram_3)?
    • What is the test bench for ram_3?
  31. HMUV-Module-31
    • What is the Register Banks?
    • What is the structure of MIPS 32 register bank and what are the different examples of register file operations?
    • What is the test bench for verifying the operations of a register file?
  32. HMUV-Module-32
    • What is Pipelining?
    • How pipelining helps in real life and can the processor pipeline concept be extended to hardware?
    • How does the k-stage synchronous pipeline look like, what is the structure of pipeline and what is a Reservation table data structure?
    • How to compute speed and efficiency of a pipeline and what is clock skew, jitter and setup time?
  33. HMUV-Module-33
    • How is pipeline modeling illustrated with the help of a simple example?
    • How to write the code for the modeled pipeline in Verilog?
    • How to write the test bench for the modeled pipeline?
  34. HMUV-Module-34
    • What are the different computation stages in a complex pipeline modeling example?
    • What are the assumptions in a complex pipeline modeling example and how does the overall pipeline diagram look like?
    • What is the clocking issue in Pipeline and what is the Verilog code for modeled pipeline?
    • How to write the test bench for the modeled pipeline?
  35. HMUV-Module-35
    • What is the switch level circuit?
    • What are the various switch level primitives in Verilog and what are NMOS, PMOS and CMOS switches?
    • How are these switches implemented to form CMOS inverter and CMOS NAND gate?
    • How are these switches implemented to form Pseudo-NMOS NOR gate and CMOS 2X1 multiplexer and what are bidirectional switches?
  36. HMUV-Module-36
    • How to implement a CMOS 4X1 Multiplexer using bidirectional Switches?
    • How to implement a Full Adder using Transistor level modeling?
    • How to write the test bench for a modeled full adder?
  37. HMUV-Module-37
    • What is the Reduced Instruction Set Architecture (RISC) and MIPS32?
    • What is the instruction set of MIPS32 being used?
    • How are MIPS instructions being encoded?
  38. HMUV-Module-38
    • What is the instruction cycle of MIPS32?
    • What is Instruction Fetch (IF) and Instruction Decode?
    • What is Execution/Effective Address Communication step (EX), Memory Access/Branch Completion (MEM) step and Register Write Back (WB) step?
    • How are the instructions executed?
  39. HMUV-Module-39
    • What are the basic requirements for pipelining MIPS32 data path?
    • How to modify Micro-operations for Pipelined MIPS32?6 mins
    • What is the micro-operation for the IF stage of pipeline implementation?
    • What is the micro-operation for the ID and EX-stages of pipeline implementation?
    • What is the micro-operation for the WB stage of pipeline implementation?
  40. HMUV-Module-40
    • How are instructions executed in a pipeline?
    • How to translate the pipelining of MIPS32 into Verilog code?
    • What are IF and ID Stage?
    • What is EX, IF, MEM and WB Stage?
  41. HMUV-Module-41
    • How to write a program to add three numbers stored in MIPS32 processor register?
    • How to write Test Bench for the addition program?
    • How to write a program to load a word, storing it in the different memory location and how to write it's test bench?
    • How to write a program to compute the factorial of N?
    • How to write the test bench for the factorial program?
  42. Hardware Modeling Using Verilog - Final Quiz
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